Let performance thrive: Intel® Conference 2013

Join us for the free conference with keynote addresses by James Reinders, director and chief evangelist for Intel® Software, and Jim Jeffers, senior product engineer for Intel® Many Integrated Core architecture. The authors will introduce new programming models for the Intel® Xeon Phi™ coprocessor and Intel® Xeon® from their latest book.

Explore the techniques and tools that can get your applications to market faster—and help increase performance and accuracy. This intensive one-day conference is designed for C, C++, and Fortran developers.

See full agenda ›

Santa Clara, CA

Santa Clara, CA

March 5, 2013

Register

Intel Corporation

3600 Juliette Lane
Santa Clara, CA 95054

Houston, TX

Houston, TX

March 26, 2013

Register

WesternGeco

10001 Richmond Avenue
Houston, TX 77042

Iselin, NJ

Iselin, NJ

April 30, 2013

Register

Microsoft

101 Wood Avenue South
Suite 900
Iselin, NJ 08830

Boston, MA

Boston, MA

May 1, 2013

Register

Microsoft

1 Cambridge Center
Cambridge, MA 02142

Questions?

For event questions, please contact Michael Markham at: michael.c.markham@intel.com

  • 8:00 - 8:50 a.m.

    Registration and Continental Breakfast

  • 8:50 - 9:00 a.m.

    Welcome and Introduction

  • 9:00 - 10:00 a.m.

    Keynote: Four Reasons the Importance of Parallel Programming is Rising

    Abstract: We are emerging from an era of early adopters to see parallel programming expand its reach and importance. The keynote will address the rising role of parallelism and four key factors that are helping speed its growth: better tools, better programming models, significantly more hardware parallelism, and better educated programmers. We’ll explore the role Intel and other companies have been playing in driving each of these four areas. Finally, we’ll provide a context for the conference sessions examining better tools and models for parallel programming.

  • 10:00 - 10:45 a.m.

    Identifying and Modeling Parallel Software: Intel® Advisor XE 2013

    Abstract: Intel® Advisor XE 2013 is the first tool for novices and experts for adding parallelism to software. In this session, we demonstrate the straightforward Intel Advisor XE workflow. First, the tool surveys or collects performance data and identifies code regions likely to benefit from parallelism. Next, the code is annotated to indicate parallel regions to the Intel Advisor XE analysis utility. Intel Advisor XE will execute the annotated code to model the potential performance gains of running the annotated regions in parallel and report out those potential gains. Finally, Intel Advisor XE models the correctness to identify any potential data conflicts or data races so the developer can choose how to address them. Intel Advisor XE supports C, C++, Fortran, and C#.

  • 10:45 - 11:00 a.m.

    Break

  • 11:00 - 11:45 a.m.

    Design: Optimize, Vectorize, and Parallelize—Intel® Composer XE 2013

    Abstract: Intel® Composer XE 2013 provides the industry's most advanced optimizing compilers, along with easy-to-use parallel program models and performance libraries designed to extract the maximum performance available from today's multicore architectures and the new Intel® Many Integrated Core Architecture (Intel® MIC). Intel Composer XE enables programmers of all skill levels to succeed in parallelization and vectorization, the two cornerstones of the multicore revolution. Unlike complex GPU models, parallel programming for multicore Intel® architecture involves straightforward extensions to programmers' existing skills, making it accessible to everyone. In this presentation, we examine simple extensions to existing C, C++, and Fortran languages to enable parallelization and vectorization.

  • 11:45 a.m. - 12:45 p.m.

    Complimentary Lunch

  • 12:45 - 1:30 p.m.

    Debug for Correctness—Find Memory and Thread Errors Using Intel® Parallel Inspector XE

    Abstract: Together, Intel® Inspector XE 2013 and Intel® Parallel Studio XE 2013 provide the best of static and dynamic analysis. Intel Inspector XE finds common threading data race issues and takes the developer directly to the source code where the race conflict occurs. Developers of threaded software will value this tool to improve code quality. However, data races are not the only type of memory errors that may be present in software. The dynamic memory analysis feature identifies common memory errors, such as buffer overruns, memory leaks, and mismatched memory allocation calls. The static analysis feature considers more execution paths than you could write test cases for—in order to identify common memory errors. The reporting mechanism clearly indicates priority or severity and allows a team to manage the reports for merging into their development environment.

  • 1:30 - 2:15 p.m.

    Analysis: Measuring System Performance, Workload Balance, and Code Efficiency—Intel® VTune™ Amplifier XE 2013

    Abstract: Intel® VTune™ Amplifier XE 2013, a superb performance analysis tool, offers numerous analysis methods and helps all developers. Intel VTune Amplifier XE offers the popular hotspots analysis and call stack information most developers use to begin performance analysis. The locks and waits is widely used to identify workload imbalance. The hardware collectors really help serious developers understand details of execution on the processor.

  • 2:15 - 2:30 p.m.

    Break

  • 2:30 - 2:45 p.m.

    Closing

  • 2:45 - 3:45 p.m.

    Q&A

  • James Reinders

    James Reinders

    Director and Parallel Programming Evangelist and
    Senior Engineer, Intel

    Conferences: Keynote presenter in Santa Clara, CA and Houston, TX

    James is involved in multiple efforts at Intel to bring parallel programming models to the software industry—including models for the Intel® Many Integrated Core (Intel® MIC) architecture. He joined Intel Corporation in 1989, and has contributed to numerous projects including the world's first TeraFLOP/s supercomputer (ASCI Red) and the world's first TeraFLOP/s microprocessor (Intel® Xeon Phi™ coprocessor). James has authored technical books, including VTune™ Performance Analyzer Essentials (Intel Press, 2005), Intel® Threading Building Blocks (O'Reilly Media, 2007), Structured Parallel Programming (Morgan Kaufmann, 2012), and Intel® Xeon Phi™ Coprocessor High Performance Programming (Morgan Kaufmann, 2013).

  • Jim Jeffers

    Jim Jeffers

    Intel® Many Integrated Core (Intel® MIC) Software Product Application Engineer

    Conferences: Keynote presenter in Iselin, NJ, and Boston, MA

    Jim focuses on enabling customers with Intel® MIC architecture products. He has more than 25 years of experience in design, implementation, and technical team leadership for high performance computing and multimedia products. As a member of the foundational Intel MIC architecture team, Jim helped define the product roadmap and led the initial phases of the device software stack development and the software performance team. Jim’s notable prior work includes contributing to the development of the imaging technology behind the virtual "first down line" on American football TV broadcasts. Jim has three granted U.S. patents.

  • Gary Carleton

    Gary Carleton

    Senior Staff Software Engineer, Intel

    Conference: Santa Clara, CA

    Sessions

    • Analysis: Measuring System Performance, Workload Balance, and Code Efficiency—Intel® VTune™ Amplifier XE 2013
    • Design: Optimize, Vectorize, and Parallelize—Intel® Composer XE 2013

    Gary has been at Intel for 27 years and currently works on software performance tools, including the Intel® VTune™ Amplifier XE profiler, and Intel® Parallel Studio XE. He has worked as an engineering manager and software engineer for Intel Corporation, Cadre Technologies, and Kaiser Engineers. Gary holds a B.S. in electrical engineering and computer sciences from the University of California at Berkeley.

  • Robert Chesebrough

    Robert Chesebrough

    Technical Compiler Engineer, Intel

    Conferences: Iselin, NJ and Boston, MA

    Sessions

    • Design: Optimize, Vectorize, and Parallelize—Intel® Composer XE 2013
    • Debug for Correctness—Find Memory and Thread Errors Using Intel® Parallel Inspector XE

    Robert has been at Intel for 13 years. He is responsible for Intel® Cilk™ Plus and vectorization enabling, as well as external training on compiler products. Prior to his current role, Robert led efforts in Intel’s academic program to encourage and support parallel programming adoption into university curriculum worldwide. He has extensive experience training software developers on technical topics. Robert is the author of the "Intel® Compiler Black-Belt Users Guide to Undocumented Switches". He holds a B.S. in physics from the University of New Mexico, and has been a software developer for more than 25 years for the U.S. DOE, Sandia National Labs, Los Alamos National Labs, and SBS technologies (aerospace).

  • Mark Davis

    Mark Davis

    Senior Principal Engineer, Intel

    Conferences: Iselin, NJ and Boston, MA

    Sessions

    • Identifying and Modeling Parallel Software: Intel® Advisor XE 2013
    • Analysis: Measuring System Performance, Workload Balance, and Code Efficiency—Intel® VTune™ Amplifier XE 2013

    As a senior principal engineer for the technical computing, analyzers, and runtimes team, Mark designs and implements software development tools for parallelism. Previously, he was architect and co-manager of the Intel® Itanium® compiler development team, providing high-quality, high-performance compilers for enterprise-class Itanium platforms. In his career, Mark has specialized in compiler optimizations, language design (Ada), performance analysis, and architecture. He earned his Ph.D. in computer science from Harvard University.

  • Ronald W. Green

    Ronald W. Green

    Manager, HPC and Fortran Compiler Support, Intel

    Conference: Houston, TX

    Sessions

    • Identifying and Modeling Parallel Software: Intel® Advisor XE 2013
    • Design: Optimize, Vectorize, and Parallelize—Intel® Composer XE 2013

    Ronald specializes in massively parallel software development and systems architectures. He has been active in technical computing and high performance computing since 1987, and has participated in getting three systems into the Top 5 of the HPC TOP500 list over the course of his career. Ronald joined Intel in 2005, and currently manages compiler support from Intel's Rio Rancho, New Mexico facility. Aside from his management responsibilities, Ronald helps run compiler and tools beta programs, moderates Intel® Software User Forums, contributes to compiler online documentation and samples, and helps with future product definition for Intel® Compiler products. Most recently, he has been assisting with the early test and launch of the compiler products supporting the Intel® Xeon Phi™ coprocessor. He holds an M.S. in computer engineering from the University of Southern California.

  • Victoria Gromova

    Victoria Gromova

    Software Engineer, Intel

    Conference: Santa Clara, CA

    Sessions

    • Identifying and Modeling Parallel Software: Intel® Advisor XE 2013
    • Debug for Correctness—Find Memory and Thread Errors Using Intel® Parallel Inspector XE

    Victoria has worked as a software engineer at Intel for more than ten years. She is an expert in multithreading and performance analysis.

  • Mike D’Mello

    Mike D’Mello

    Program Manager, Tools Immersion Program, Intel

    Conference: Houston, TX

    Sessions

    • Analysis: Measuring System Performance, Workload Balance, and Code Efficiency—Intel® VTune™ Amplifier XE 2013
    • Debug for Correctness—Find Memory and Thread Errors Using Intel® Parallel Inspector XE

    For the last ten years, Michael has been focused on tool-based approaches to software optimization. Prior to joining Intel in 2003, Michael held various technical positions at the Hewlett-Packard Company, Convex Computer Corporation, and Thinking Machines Corporation. He has more than 20 years of experience in the parallel computing industry. Michael received a Ph.D. in chemical physics from the University of Texas at Austin.